[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: simplify ME lock and memory enable bit write

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37971 )

Change subject: nb/intel/sandybridge: simplify ME lock and memory enable bit write
......................................................................

nb/intel/sandybridge: simplify ME lock and memory enable bit write

Timeless build results in identical image for X230.

Change-Id: I36842ebd4917e96aa8aec87ba13d27bd4bf44b76
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37971
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 8f58dcb..b12ea25 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -608,9 +608,8 @@
    	reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK);
    	val = (0x80000 - me_uma_size) & 0xfff;
    	reg = (reg & ~0xfff00000) | (val << 20);
-		reg = (reg & ~0x400) | (1 << 10);	// set lockbit on ME mem
-
-		reg = (reg & ~0x800) | (1 << 11);	// set ME memory enable
+		reg = reg | (1 << 10);	// set lockbit on ME mem
+		reg = reg | (1 << 11);	// set ME memory enable
    	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg);
    	pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg);
    }