[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes

[Felix Singer (Code Review)]

Attention is currently required from: Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu.

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )

Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................

Patch Set 33:

(6 comments)

File src/soc/intel/xeon_sp/gnr/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/81316/comment/d3053b2a_0c4a3ae3 :
PS33, Line 12: romstage-y += romstage.c soc_util.c
             : romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
             : 
             : ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c
             : ramstage-y += ../chip_gen6.c
             : 
             : CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr/include -I$(src)/soc/intel/xeon_sp/gnr
             : 
Use one value per line

File src/soc/intel/xeon_sp/gnr/chip.h:

https://review.coreboot.org/c/coreboot/+/81316/comment/4166b458_5aa042b2 :
PS33, Line 16: 	u
Use bool where possible.

File src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/81316/comment/7f18486f_b25e6528 :
PS33, Line 184: // IIO DFX Global D7F7 registers
              : #define IIO_DFX_TSWCTL0 0x30c
              : #define IIO_DFX_LCK_CTL 0x504
              : 
              : // XHCI register
              : #define SYS_BUS_CFG2 0x44
              : 
              : /*
Please be consistent with comment style.

File src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h:

https://review.coreboot.org/c/coreboot/+/81316/comment/5f2285c4_4506ed1e :
PS33, Line 3: // TEMPORARY PLACE HOLDER! DO NOT USE!
Eh?

File src/soc/intel/xeon_sp/gnr/soc_util.c:

https://review.coreboot.org/c/coreboot/+/81316/comment/4780b99a_9f9d5379 :
PS33, Line 143: bool is_memtype_reserved(uint16_t mem_type)
              : {
              : 	return FALSE;
              : }
              : 
              : bool is_memtype_non_volatile(uint16_t mem_type)
              : {
              : 	return FALSE;
              : }
              : 
              : bool is_memtype_processor_attached(uint16_t mem_type)
              : {
              : 	return TRUE;
              : }
              : 
Please use true/false, the definitions from coreboot.

File src/soc/intel/xeon_sp/uncore.c:

PS33: 
The code movements should be separated out into their own commit.