[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46357 )

Change subject: soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c
......................................................................

soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c

Other Intel northbridges have this function in this file.

Change-Id: I9f084e760ec438d662484455212b5c40a8448928
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46357
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/broadwell/memmap.c
M src/soc/intel/broadwell/romstage/romstage.c
2 files changed, 14 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index e4c787a..f7e58af 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -3,6 +3,7 @@
 /* Use simple device model for this file even in ramstage */
 #define __SIMPLE_DEVICE__

+#include <arch/romstage.h>
 #include <cbmem.h>
 #include <cpu/x86/smm.h>
 #include <device/pci.h>
@@ -43,3 +44,16 @@
    *start = tseg;
    *size = bgsm - tseg;
 }
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+	uintptr_t top_of_ram;
+
+	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+	 * above top of the ram. This satisfies MTRR alignment requirement
+	 * with different TSEG size configurations.
+	 */
+	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
+			MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 3b7aa40..83e5b73 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -16,19 +16,6 @@
 #include <soc/romstage.h>
 #include <soc/spi.h>

-void fill_postcar_frame(struct postcar_frame *pcf)
-{
-	uintptr_t top_of_ram;
-
-	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
-	 * above top of the ram. This satisfies MTRR alignment requirement
-	 * with different TSEG size configurations.
-	 */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
-	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
-			MTRR_TYPE_WRBACK);
-}
-
 /* Entry from cpu/intel/car/romstage.c. */
 void mainboard_romstage_entry(void)
 {