Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43000 )
Change subject: post_code: add missing postcode calls ......................................................................
post_code: add missing postcode calls
The change adds postcode calls wherever necessary on top of the updated set of postcode defines
Change-Id: Ia75cd863bf6ffac2c91ff78aefabc5327b1c138b Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net --- M src/arch/x86/postcar_loader.c M src/console/init.c M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/haswell/romstage.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/cache_as_ram.S M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/xeon_sp/romstage.c 10 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/43000/1
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index f79c90c..7b3088f 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -104,6 +104,7 @@
postcar_frame_common_mtrrs(pcf);
+ post_code(POST_ENTRY_POST_CAR); run_postcar_phase(pcf); /* We do not return here. */ } diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad..cfe2e2e 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -62,6 +62,7 @@
asmlinkage void console_init(void) { + post_code(POST_CONSOLE_READY); init_log_level();
if (CONFIG(DEBUG_CONSOLE_INIT)) diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 7a96441..e0cebc1 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -20,6 +20,7 @@ xor %edx, %edx
clear_fixed_mtrr: + post_code(POST_CAR_FIXED_MTRR) add $-2, %ebx movzwl fixed_mtrr_list(%ebx), %ecx wrmsr diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 6481404..6ddcf19 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,6 +23,7 @@ andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax jz ap_init
+ post_code(POST_CAR_FIXED_MTRR) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 35566c4..f3090e7 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -18,6 +18,7 @@ int boot_mode; int wake_from_s3;
+ post_code(POST_ENTRY_ROMSTAGE); enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..4a65cab 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -84,6 +84,7 @@ postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE); recover_postcar_frame(&pcf, cb->s3resume);
+ post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); /* We do not return. */ } diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 2a7678e..8ffcbcc 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -51,12 +51,14 @@ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr
+ post_code(POST_CAR_INIT_CACHE) /* Enable cache */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0
+ post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index aa7d677..aaa7f81 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -363,6 +363,7 @@
pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); + post_code(POST_ROM_SDRAM_INIT); sdram_initialize(&pei_data);
/* Sanity check mrc_var location by verifying a known field */ diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 5932fe6..69633ae 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -87,6 +87,7 @@ movd %mm1, %eax push %eax
+ post_code(POST_ENTRY_C_BOOTBLOCK) /* We can call into C functions now */ call bootblock_c_entry
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 02ed7eb..86e121e 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -41,6 +41,7 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); }