Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45184
to look at the new patch set (#2).
Change subject: cpu/intel/model_1067x: enable PECI ......................................................................
cpu/intel/model_1067x: enable PECI
This is required for Super I/Os to be able to read the CPU temperature through PECI.
On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default. This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested workaround is "Do not initialize PECI before processor update is loaded". Since coreboot performs microcode updates before running this code it should not cause any trouble. It was tested on a Core 2 Duo E8400, stepping E0.
PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium Dual-Core E2160.
See commit edac28ce65e48d6b2a0a2421d046a4fe4b2bf589 for the same change on cpu/intel/model_6fx.
Signed-off-by: Michael Büchler michael.buechler@posteo.net Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6 --- M src/cpu/intel/model_1067x/model_1067x_init.c 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/45184/2