Attention is currently required from: Felix Singer, Erik van den Bogaert, Michał Żygowski, Frans Hendriks, Michael Niewöhner, Patrick Rudolph, Piotr Król. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60722 )
Change subject: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config ......................................................................
soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config
Lists of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards selects DISABLE_CSE_AT_PRE_BOOT config to make CSE function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`.
Mainboards that choose to make CSE enable during boot don't select `cse disable` config.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/Kconfig M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c 32 files changed, 15 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60722/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index ac1b45d..ab8787c 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -47,7 +47,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 3a55f9e..096089f 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select DISABLE_CSE_AT_PRE_BOOT select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index aed9184..a45127c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -101,9 +101,6 @@ device pci 15.3 off end # I2C #3 device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 - - # FIXME: does not match devicetree! - register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index db4d1ac..d22f574 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -60,9 +60,7 @@ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left end device ref thermal on end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref sata on register "SataSalpSupport" = "0" # Ports diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 50738f4..f5d860d 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -4,6 +4,7 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select DISABLE_ACPI_HIBERNATE + select DISABLE_CSE_AT_PRE_BOOT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 023ace9..05bcc12 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0"
register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ @@ -224,6 +223,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 007cbc7..6720681 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_MAX98927 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c731005..1e9ffd9 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -43,7 +43,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index afb2831..3f7147e 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_I2C_GENERIC select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index ceca5f1..5ecc77b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -74,7 +74,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 04a48f7..f996bcb 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index a200cfb..9a3e619 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -42,7 +42,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 4a19f86..64ce0a6 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 39b7d9f..d26f6bd 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -50,7 +50,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4d145e1..db4aeeb 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -38,7 +38,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 6d7541e..7609e00 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -37,7 +37,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 068a031..b8a1812 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -38,7 +38,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index e4e0158..03336f2 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -43,7 +43,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ff06d6a..c6c2d3d 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -50,7 +50,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 9be000f..5c34792 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -38,7 +38,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 2abf832..6e66ef2 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -1,6 +1,7 @@ config BOARD_INTEL_KBLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b7..bae619811 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ register "dptf_enable" = "1"
# FSP Configuration - register "HeciEnabled" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 85f9e54..2ef19d1 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ba4835e..deb9f38 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -25,7 +25,6 @@ register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index d047f76..39c2e33 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -46,7 +46,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index a264c6b..feb8b9f 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,7 +34,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 4c6f6a8..b989188 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -1,6 +1,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_GENERIC_CBFS_SERIAL select GFX_GMA_IGNORE_PRESENCE_STRAPS select HAVE_ACPI_RESUME diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index dfa894b..ef898b2 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -52,7 +52,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 3d311a3..3b2343b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -31,7 +31,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a048699..2e4e88c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -410,11 +410,11 @@ tconfig->PowerLimit4 = 0; /* * To disable HECI, the Psf needs to be left unlocked - * by FSP till end of post sequence. Based on the devicetree + * by FSP till end of post sequence. Based on the config * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; + tconfig->PchSbAccessUnlock = CONFIG(DISABLE_CSE_AT_PRE_BOOT);
const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; tconfig->PchLockDownBiosInterface = lockdown_by_fsp; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 08d5d0f..12a6ae97 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -395,11 +395,6 @@ * 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; - /* - * HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS - */ - u8 HeciEnabled;
/* * Enable VR specific mailbox command diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 83bd3ae..28fbfa9 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -62,8 +62,8 @@ */ pch_thermal_configuration();
- /* we should disable Heci1 based on the devicetree policy */ - if (config->HeciEnabled == 0) + /* we should disable Heci1 based on the config */ + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT)) pch_disable_heci();
/* Hide p2sb device as the OS must not change BAR0. */