Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70265 )
Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ......................................................................
soc/intel/xeon_sp: Read ioapic configuration from hardware
This more robust than hardcoding whathever FSP has set up and is a lot less code.
Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 5 files changed, 33 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70265/1
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 860c868..050facf 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -73,33 +73,27 @@ return current; }
-__weak const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries) +static const uintptr_t default_ioapic_bases[] = { IO_APIC_ADDR }; + +__weak size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) { - *entries = 0; - return NULL; + *ioapic_bases = default_ioapic_bases; + return ARRAY_SIZE(default_ioapic_bases); }
unsigned long acpi_fill_madt(unsigned long current) { - const struct madt_ioapic_info *ioapic_table; + const uintptr_t *ioapic_table; size_t ioapic_entries;
/* Local APICs */ current = acpi_create_madt_lapics_with_nmis(current);
/* IOAPIC */ - ioapic_table = soc_get_ioapic_info(&ioapic_entries); - if (ioapic_entries) { - for (int i = 0; i < ioapic_entries; i++) { - current += acpi_create_madt_ioapic( - (void *)current, - ioapic_table[i].id, - ioapic_table[i].addr, - ioapic_table[i].gsi_base); - } - } else { + ioapic_entries = soc_get_ioapic_info(&ioapic_table); + for (int i = 0; i < ioapic_entries; i++) { /* Default SOC IOAPIC entry */ - current += acpi_create_madt_ioapic_from_hw((void *)current, IO_APIC_ADDR); + current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); }
return acpi_madt_irq_overrides(current); diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index d05ddf3..fb4b096 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -93,17 +93,11 @@ */ int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio);
-struct madt_ioapic_info { - u8 id; - u32 addr; - u32 gsi_base; -};
/* - * Returns a table of MADT ioapic_info entries and the number of entries - * If the SOC doesn't implement this hook a default ioapic setting is used. + * Return the number of table entires and takes a pointer to an array of ioapic bases. */ -const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries); +size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]);
struct soc_pmc_lpm { unsigned int num_substates; diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 2abe433..81f50a2 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -87,41 +87,19 @@ return map; }
-static void print_madt_ioapic(int socket, int stack, - int ioapic_id, uint32_t ioapic_base, int gsi_base) -{ - printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - socket, stack, ioapic_id, ioapic_base, gsi_base); -} +static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1];
-const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries) +size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) { - int cur_index; - int gsi_per_iiostack = 0; - + int index = 0; const IIO_UDS *hob = get_iio_uds();
- uint8_t gsi_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1] = { 0 }; + *ioapic_bases = xeonsp_ioapic_bases;
- for (uint8_t i = 1; i < sizeof(gsi_bases); i++) { - int gsi_base = CONFIG_XEON_SP_PCH_IOAPIC_GSI_BASES; - gsi_bases[i] = gsi_base + (i * gsi_per_iiostack); - } - - static struct madt_ioapic_info madt_tbl[ARRAY_SIZE(gsi_bases)]; - - cur_index = 0; - madt_tbl[cur_index].id = PCH_IOAPIC_ID; - madt_tbl[cur_index].addr = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase; - madt_tbl[cur_index].gsi_base = gsi_bases[cur_index]; - print_madt_ioapic(0, 0, madt_tbl[cur_index].id, - madt_tbl[cur_index].addr, madt_tbl[cur_index].gsi_base); - ++cur_index; + xeonsp_ioapic_bases[index++] = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase;
if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) { - *entries = cur_index; - return madt_tbl; + return index; }
for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { @@ -130,25 +108,10 @@ &hob->PlatformData.IIO_resource[socket].StackRes[stack]; if (!is_iio_stack_res(ri)) continue; - assert(cur_index < ARRAY_SIZE(gsi_bases)); - madt_tbl[cur_index].id = soc_get_iio_ioapicid(socket, stack); - madt_tbl[cur_index].gsi_base = gsi_bases[cur_index]; - madt_tbl[cur_index].addr = ri->IoApicBase; - - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * The IIO IOAPIC is placed at 0x1000 from the reported base. - */ - if (stack == 0 && socket == 0) - madt_tbl[cur_index].addr += 0x1000; - - print_madt_ioapic(socket, stack, madt_tbl[cur_index].id, - madt_tbl[cur_index].addr, - madt_tbl[cur_index].gsi_base); - ++cur_index; + assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); + xeonsp_ioapic_bases[index++] = ri->IoApicBase; } }
- *entries = cur_index; - return madt_tbl; + return index; } diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 52de09a..aa344ce 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -112,10 +112,6 @@ bool default y
-config XEON_SP_PCH_IOAPIC_GSI_BASES - hex - default 0x78 - if INTEL_TXT
config INTEL_TXT_SINIT_SIZE diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index c325512..18e5f2f5 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -63,8 +63,4 @@ bool default y
-config XEON_SP_PCH_IOAPIC_GSI_BASES - hex - default 0x18 - endif