4 Jun
2019
4 Jun
'19
2:57 a.m.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33174 )
Change subject: nb/intel/sandybridge/mrc.bin: Increase the CAR size ......................................................................
Patch Set 3: Code-Review-1
(1 comment)
I assume this breaks offset DCACHE_RAM_VAR_BASE in raminit-mrc:268. Or you could just remove the runtime test lines 408-418 since there is clean separation now.
https://review.coreboot.org/#/c/33174/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33174/3//COMMIT_MSG@13 PS3, Line 13: the DCACHE_RAM_MRC_VAR_SIZE. .. the heap/pool of mrc.bin falls in ..
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ida8ad9a54d29a9ee1301bdcff00d81f548d2b81e
Gerrit-Change-Number: 33174
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