[coreboot-gerrit] Change in coreboot[master]: mb/intel/tglrvp: Add memory config for Tiger Lake UP4

[Srinidhi N Kaushik (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39365

to look at the new patch set (#3).

Change subject: mb/intel/tglrvp: Add memory config for Tiger Lake UP4
......................................................................

mb/intel/tglrvp: Add memory config for Tiger Lake UP4

Add LPDDR4 memory configuration for Tiger Lake UP4 platform which
includes
1. DQ/DQs Mapping
2. Board id Support
3. SPD indexing

BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully

Signed-off-by: Srinidhi N Kaushik 
Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e
---
M src/mainboard/intel/tglrvp/board_id.h
M src/mainboard/intel/tglrvp/romstage_fsp_params.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
3 files changed, 31 insertions(+), 23 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39365/3