Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39234 )
Change subject: sc7180: clock: Add support to bump CPU levels ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39234/1/src/soc/qualcomm/sc7180/clo... File src/soc/qualcomm/sc7180/clock.c:
https://review.coreboot.org/c/coreboot/+/39234/1/src/soc/qualcomm/sc7180/clo... PS1, Line 314: udelay(1);
Could this be an endless loop?
Sure, I could make it counter based.
https://review.coreboot.org/c/coreboot/+/39234/1/src/soc/qualcomm/sc7180/clo... PS1, Line 326: pll_init_and_set(apss_silver, L_VAL_1516P8MHz);
Print an information/debug message, that the speed was increased?
Would print the information.