Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52302 )
Change subject: soc/amd/piasso/fch: use common pm_set_power_failure_state functionality ......................................................................
soc/amd/piasso/fch: use common pm_set_power_failure_state functionality
The functionality to restore the previous power state after power was lost that could previously be enabled by selecting MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's Kconfig instead.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/early_fch.c M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/include/soc/southbridge.h 4 files changed, 2 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/52302/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b464539..1918cb7 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -331,14 +331,6 @@ functionality isn't disabled, configuring it as an output and driving it as 0 will cause a reset.
-config MAINBOARD_POWER_RESTORE - def_bool n - help - This option determines what state to go to once power is restored - after having been lost in S0. Select this option to automatically - return to S0. Otherwise the system will remain in S5 once power - is restored. - config FSP_TEMP_RAM_SIZE hex default 0x40000 diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 5f47638..88011c1 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -4,6 +4,7 @@ #include <amdblocks/espi.h> #include <amdblocks/i2c.h> #include <amdblocks/lpc.h> +#include <amdblocks/pmlib.h> #include <amdblocks/smbus.h> #include <amdblocks/spi.h> #include <console/console.h> @@ -71,6 +72,7 @@ /* After console init */ void fch_early_init(void) { + pm_set_power_failure_state(); fch_print_pmxc0_status(); i2c_soc_early_init();
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 261fea5..b65bc6f 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -239,11 +239,6 @@
void fch_final(void *chip_info) { - uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; - - if (CONFIG(MAINBOARD_POWER_RESTORE)) - restored_power = PM_RESTORE_S0_IF_PREV_S0; - pm_write8(PM_RTC_SHADOW, restored_power); }
/* diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index ede2108..e2a069b 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -32,10 +32,6 @@ #define PM_SERIRQ_MODE BIT(6) #define PM_SERIRQ_ENABLE BIT(7)
-#define PM_RTC_SHADOW 0x5b /* state when power resumes */ -#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */ -#define PM_RESTORE_S0_IF_PREV_S0 0x07 /* S0 if previously at S0 */ - #define PM_EVT_BLK 0x60 #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ #define PCIEXPWAK_STS BIT(14)