Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40694 )
Change subject: soc/intel/apl: Add panel power and backlight configuration ......................................................................
soc/intel/apl: Add panel power and backlight configuration
Change-Id: Id8892ac7aafce1006831e2d9f2806919f5950756 Signed-off-by: Nico Huber nico.huber@secunet.com --- M src/drivers/intel/gma/i915_reg.h M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/graphics.c 3 files changed, 117 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/40694/1
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 4ebdc59..e0381c5 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -1705,6 +1705,33 @@ #define BLM_PCH_POLARITY (1 << 29) #define BLC_PWM_PCH_CTL2 0xc8254
+#define UTIL_PIN_CTL 0x48400 +#define UTIL_PIN_ENABLE (1 << 31) + +#define UTIL_PIN_PIPE(x) ((x) << 29) +#define UTIL_PIN_PIPE_MASK (3 << 29) +#define UTIL_PIN_MODE_PWM (1 << 24) +#define UTIL_PIN_MODE_MASK (0xf << 24) +#define UTIL_PIN_POLARITY (1 << 22) + +/* BXT backlight register definition. */ +#define _BXT_BLC_PWM_CTL1 0xC8250 +#define BXT_BLC_PWM_ENABLE (1 << 31) +#define BXT_BLC_PWM_POLARITY (1 << 29) +#define _BXT_BLC_PWM_FREQ1 0xC8254 +#define _BXT_BLC_PWM_DUTY1 0xC8258 + +#define _BXT_BLC_PWM_CTL2 0xC8350 +#define _BXT_BLC_PWM_FREQ2 0xC8354 +#define _BXT_BLC_PWM_DUTY2 0xC8358 + +#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \ + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \ + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \ + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) + /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ac36b70..a952ec0 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -36,11 +36,34 @@ PNP_PERF_POWER, };
+struct soc_intel_apl_pp { + unsigned int up_delay_ms; + unsigned int down_delay_ms; + unsigned int cycle_delay_ms; + unsigned int backlight_on_delay_ms; + unsigned int backlight_off_delay_ms; +}; + +struct soc_intel_apl_blc { + unsigned int pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } polarity; +}; + struct soc_intel_apollolake_config {
/* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config;
+ /* IGD panel configuration */ + struct soc_intel_apl_pp gpu_pp[2]; + /* Second backlight control shares logic with other pins (aka. display + utility pin). Be sure it's used for PWM before setting any value for + the secondary controls. */ + struct soc_intel_apl_blc gpu_blc[2]; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 033b300..2feedf7 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -16,23 +16,90 @@ #include <stdint.h> #include <arch/acpi.h> #include <bootmode.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/graphics.h> +#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/opregion.h> #include <drivers/intel/gma/libgfxinit.h> #include <types.h>
+#include "chip.h" + uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); }
+static void graphics_configure_panelpower( + const struct soc_intel_apl_pp *const pp, + uint8_t *const mmio, const unsigned int i) +{ + const unsigned int offset = i * 0x100; + uint32_t reg32; + + reg32 = ((DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) & 0x1f) | PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL + offset, reg32); + + reg32 = pp->up_delay_ms * 10 << 16; + reg32 |= pp->backlight_on_delay_ms * 10; + write32(mmio + PCH_PP_ON_DELAYS + offset, reg32); + + reg32 = pp->down_delay_ms * 10 << 16; + reg32 |= pp->backlight_off_delay_ms * 10; + write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32); +} + +static void graphics_configure_backlight( + const struct soc_intel_apl_blc *const blc, + uint8_t *const mmio, const unsigned int i) +{ + if (!blc->pwm_hz) + return; + + const unsigned int pwm_period = 19200 * 1000 / blc->pwm_hz; + write32(mmio + BXT_BLC_PWM_FREQ(i), pwm_period); + write32(mmio + BXT_BLC_PWM_DUTY(i), pwm_period / 2); /* Start with a 50% duty cycle. */ + write32(mmio + BXT_BLC_PWM_CTL(i), + (blc->polarity ? BXT_BLC_PWM_POLARITY : 0)); + + /* Second backlight control uses display utility pin. */ + if (i == 1) { + write32(mmio + UTIL_PIN_CTL, 0); /* Make sure it's disabled, don't know + what FSP might have done already. */ + write32(mmio + UTIL_PIN_CTL, UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE); + } +} + void graphics_soc_init(struct device *const dev) { + const struct soc_intel_apollolake_config *const conf = dev->chip_info; + const struct resource *mmio_res; + void *mmio; + unsigned int i; + + /* Some hardware configuration first. */ + + if (!conf) + return; + + mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!mmio_res || !mmio_res->base) + return; + mmio = (void *)(uintptr_t)mmio_res->base; + + for (i = 0; i < ARRAY_SIZE(conf->gpu_pp); ++i) + graphics_configure_panelpower(&conf->gpu_pp[i], mmio, i); + + for (i = 0; i < ARRAY_SIZE(conf->gpu_blc); ++i) + graphics_configure_backlight(&conf->gpu_blc[i], mmio, i); + + /* From here on, it's just modesetting. */ + if (CONFIG(RUN_FSP_GOP)) return;