[coreboot-gerrit] Change in coreboot[master]: timestamps: Rename timestamps to make names more consistent

[Jakub Czapiga (Code Review)]

Attention is currently required from: Raul Rangel, Jakub Czapiga, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Fred Reitberger, Yu-Ping Wu, Felix Held.
Hello build bot (Jenkins), Raul Rangel, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Fred Reitberger, Yu-Ping Wu, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62019

to look at the new patch set (#7).

Change subject: timestamps: Rename timestamps to make names more consistent
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timestamps: Rename timestamps to make names more consistent

This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.

Signed-off-by: Jakub Czapiga 
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
---
M src/arch/arm64/romstage.c
M src/arch/x86/postcar.c
M src/arch/x86/postcar_loader.c
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/cpu/intel/car/romstage.c
M src/drivers/amd/agesa/eventlog.c
M src/drivers/amd/agesa/romstage.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/vpd/vpd.c
M src/lib/bootblock.c
M src/lib/cbfs.c
M src/lib/decompressor.c
M src/lib/fit_payload.c
M src/lib/hardwaremain.c
M src/lib/prog_loaders.c
M src/lib/selfboot.c
M src/mainboard/google/daisy/romstage.c
M src/mainboard/google/nyan/romstage.c
M src/mainboard/google/nyan_big/romstage.c
M src/mainboard/google/nyan_blaze/romstage.c
M src/mainboard/google/peach_pit/romstage.c
M src/mainboard/google/veyron/romstage.c
M src/mainboard/google/veyron_mickey/romstage.c
M src/mainboard/google/veyron_rialto/romstage.c
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/ironlake/romstage.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/x4x/raminit.c
M src/security/vboot/ec_sync.c
M src/security/vboot/vboot_loader.c
M src/security/vboot/vboot_logic.c
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/common/block/apob/apob_cache.c
M src/soc/amd/common/pi/agesawrapper.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/sabrina/romstage.c
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/common/block/cse/cse_eop.c
M src/vendorcode/google/chromeos/cr50_enable_update.c
M tests/lib/timestamp-test.c
51 files changed, 274 insertions(+), 274 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62019/7