Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25287
Change subject: mainboard/google/kahlee: Update GPIOs based on board ID ......................................................................
mainboard/google/kahlee: Update GPIOs based on board ID
BUG=b:73078053 TEST=build & boot Grunt
Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 Signed-off-by: Martin Roth martinroth@chromium.org --- M src/mainboard/google/kahlee/bootblock/bootblock.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h 4 files changed, 75 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25287/1
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 1eb18f1..a7207b0 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -19,6 +19,7 @@ #include <soc/southbridge.h> #include <variant/ec.h> #include <variant/gpio.h> +#include <boardid.h>
void bootblock_mainboard_early_init(void) { @@ -30,6 +31,16 @@
gpios = variant_early_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); + + /* TODO: Remove when no longer needed */ + /* Program additional early GPIOs */ + if (board_id() < 2) { + gpios = variant_early_gpio_table_old(&num_gpios); + sb_program_gpios(gpios, num_gpios); + } else { + gpios = variant_early_gpio_table_new(&num_gpios); + sb_program_gpios(gpios, num_gpios); + } }
void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e82569e..2a1c3eb 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -30,6 +30,7 @@ #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <boardid.h>
/*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -168,6 +169,13 @@ gpios = variant_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios);
+ /* TODO: Remove when no longer needed */ + /* Reprogram additional GPIOs */ + if (board_id() < 2) { + gpios = variant_gpio_table_old(&num_gpios); + sb_program_gpios(gpios, num_gpios); + } + gpes = get_gpe_table(&num); gpe_configure_sci(gpes, num);
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index cab7611..2e0a07e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -83,9 +83,6 @@ /* GPIO_26 - APU_PCIE_RST_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
- /* GPIO_40 - EMMC_BRIDGE_RST_L - Currently unused */ - PAD_GPI(GPIO_40, PULL_UP), - /* GPIO_42 - S5_MUX_CTRL */ PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE),
@@ -110,9 +107,6 @@ /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
- /* GPIO_93 - EMMC_RST_L */ - PAD_GPO(GPIO_93, HIGH), - /* GPIO_95 - SD_CLK */ /* GPIO_96 - SD_CMD */ /* GPIO_97 - SD_D0 */ @@ -195,6 +189,22 @@ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), };
+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_new[] = { + /* GPIO_40 - EMMC_BRIDGE_RST */ + PAD_GPI(GPIO_40, PULL_DOWN), + + /* GPIO_93 - EMMC_RST */ + PAD_GPO(GPIO_93, LOW), +}; + +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_old[] = { + /* GPIO_40 - EMMC_BRIDGE_RST_L */ + PAD_GPI(GPIO_40, PULL_UP), + + /* GPIO_93 - EMMC_RST_L */ + PAD_GPO(GPIO_93, HIGH), +}; + const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), @@ -202,8 +212,8 @@ /* GPIO_10 - SLP_S0_L (currently not used) */ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),
- /* GPIO_12 - Unused (TP126) */ - PAD_GPI(GPIO_12, PULL_UP), + /* GPIO_12 - EN_PP3300_TRACKPAD */ + PAD_GPO(GPIO_12, HIGH),
/* GPIO_13 - APU_PEN_PDCT_ODL (currently not used) */ PAD_GPI(GPIO_13, PULL_UP), @@ -233,7 +243,7 @@ PAD_GPO(GPIO_90, HIGH),
/* GPIO_91 - EN_PP3300_TRACKPAD */ - PAD_GPO(GPIO_91, HIGH), + PAD_GPI(GPIO_91, PULL_UP),
/* GPIO_102 - EN_SD_SOCKET_PWR */ PAD_NF(GPIO_102, SD0_PWR_CTRL, PULL_DOWN), @@ -254,6 +264,15 @@ PAD_GPI(GPIO_135, PULL_UP), };
+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram_old[] = { + + /* GPIO_12 - Unused (TP126) */ + PAD_GPI(GPIO_12, PULL_UP), + + /* GPIO_91 - EN_PP3300_TRACKPAD */ + PAD_GPO(GPIO_91, HIGH), +}; + const __attribute__((weak)) struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) { @@ -268,6 +287,28 @@ return gpio_set_stage_ram; }
+/* TODO: Remove when no longer needed */ +const __attribute__((weak)) +struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_old(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset_old); + return gpio_set_stage_reset_old; +} + +const __attribute__((weak)) +struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_new(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset_new); + return gpio_set_stage_reset_new; +} + +const __attribute__((weak)) +struct soc_amd_stoneyridge_gpio *variant_gpio_table_old(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram_old); + return gpio_set_stage_ram_old; +} + /* * GPE setup table must match ACPI GPE ASL * { gevent, gpe, direction, level } diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index e5a348a..9744113 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -31,5 +31,11 @@ int variant_get_ehci_oc_map(uint16_t *usb_oc_map); const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size); const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size); +/* TODO: Remove when no longer needed */ +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_old( \ + size_t *size); +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_new( \ + size_t *size); +const struct soc_amd_stoneyridge_gpio *variant_gpio_table_old(size_t *size);
#endif /* __BASEBOARD_VARIANTS_H__ */