Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4687
-gerrit
commit 0db3b7b8711e242627c73ab4e0fa857e1df76b91 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sat Dec 28 15:42:31 2013 -0500
cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build failure if the bootblock is too large, and making sure romstage and ramstage cannot overlap in memory.
Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/cpu/allwinner/a10/Kconfig | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index b782b9a..fab0022 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -34,14 +34,18 @@ config CBFS_HEADER_ROM_OFFSET hex default 0x10
+# This is the maximum size bootblock that the BROM will load. If the bootblock +# gets larger, this will generate a build failure, rather than a silent +# "coreboot won't run" failure. +# Normally, we would place romstage at 0x5fe0, but we place it a little lower to +# satisfy the 64 byte alignment. config CBFS_ROM_OFFSET - # Calculated by BL1 + max bootblock size. - default 0x4c00 + default 0x5fc0
-# FIXME: untested +# 16 MiB above ramstage, so there is no overlap config ROMSTAGE_BASE hex - default SYS_SDRAM_BASE + default 0x41000000
# Keep the stack in SRAM block A2. # SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the