[coreboot-gerrit] Change in coreboot[master]: intel/i945: Call fixup_i945_errata() only for mobile version

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37188 )

Change subject: intel/i945: Call fixup_i945_errata() only for mobile version
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intel/i945: Call fixup_i945_errata() only for mobile version

Per Mobile Intel ® 945 Express Chipset Family - Specification Update
Document Number: 309220-013 (page 15), the power saving optimization
Erratum is for Mobile Intel ® 945 Express Chipset family.

So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply
that function only for I945GM.

Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/northbridge/intel/i945/errata.c
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/i945/romstage.c
3 files changed, 4 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c
index 2b9b941..4d8b999 100644
--- a/src/northbridge/intel/i945/errata.c
+++ b/src/northbridge/intel/i945/errata.c
@@ -17,7 +17,7 @@
 #include "i945.h"
 #include "raminit.h"

-int fixup_i945_errata(void)
+int fixup_i945gm_errata(void)
 {
    u32 reg32;

diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index d417169..26a1f50 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -67,5 +67,5 @@

void receive_enable_adjust(struct sys_info *sysinfo);
 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
-int fixup_i945_errata(void);
+int fixup_i945gm_errata(void);
 #endif				/* RAMINIT_H */
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
index 6274e09..2333b7d 100644
--- a/src/northbridge/intel/i945/romstage.c
+++ b/src/northbridge/intel/i945/romstage.c
@@ -76,7 +76,8 @@
    mainboard_late_rcba_config();

/* Chipset Errata! */
-	fixup_i945_errata();
+	if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+		fixup_i945gm_errata();

/* Initialize the internal PCIe links before we go into stage2 */
    i945_late_initialization(s3resume);