[coreboot-gerrit] Change in coreboot[master]: Add configurable ramstage support for minimal PCI scanning

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )

Change subject: Add configurable ramstage support for minimal PCI scanning
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Patch Set 9:
> If my hunch about ACPI is correct here, and we eventually want to keep PCI enumeration without resource allocation, we are looking at 99% revert of this commit to fix it. Cases where vendors (and/or original authors) return to their code and willingly accept reverts are unfortunately rare. I did not fix the previous regressions I caused related to hidden Intel PCI devices either, I believe ultimately Nico committed the fixes(?).

I think some people may be talking past one another. I apologize if I am off. In server world hotplug devices have a system design component that does require some ACPI code for sequencing the power, etc. In the USB4/thunderbolt world peripherals are truly hot-pluggable w/o having that specific design component. The former needs per platform handling while the latter doesn't have to.