Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42648 )
Change subject: sb/intel/i82801jx/Makefile.inc: Sort entries ......................................................................
sb/intel/i82801jx/Makefile.inc: Sort entries
Sort them by stage execution order, then alphabetically. Place more complex rules at the end.
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.
Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801jx/Makefile.inc 1 file changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42648/1
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 253a5a1..8edbf4f 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -5,23 +5,23 @@ bootblock-y += bootblock.c bootblock-y += early_init.c
-ramstage-y += i82801jx.c +romstage-y += early_init.c +romstage-y += early_smbus.c + ramstage-y += fadt.c -ramstage-y += pci.c -ramstage-y += lpc.c -ramstage-y += pcie.c -ramstage-y += usb_ehci.c -ramstage-y += sata.c ramstage-y += hdaudio.c -ramstage-y += thermal.c +ramstage-y += i82801jx.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb_ehci.c ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
smm-y += smihandler.c
-romstage-y += early_init.c -romstage-y += early_smbus.c - endif