[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add PMC ACPI interface

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55172 )

Change subject: soc/intel/alderlake: Add PMC ACPI interface
......................................................................

soc/intel/alderlake: Add PMC ACPI interface

This ACPI interface is required by e.g., the intel/common/pcie/rtd3
driver, which is used by some alderlake boards.

BUG=b:190080798
TEST=disassemble SSDT and find _SB.PCI0.PMC.IPCS

Signed-off-by: Tim Wawrzynczak 
Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0
---
M src/soc/intel/alderlake/pmc.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/55172/1

diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c
index 03399c3..6ee3ef1 100644
--- a/src/soc/intel/alderlake/pmc.c
+++ b/src/soc/intel/alderlake/pmc.c
@@ -12,6 +12,7 @@
 #include <device/device.h>
 #include <drivers/intel/pmc_mux/chip.h>
 #include <intelblocks/pmc.h>
+#include <intelblocks/pmc_ipc.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <soc/pci_devs.h>
@@ -121,6 +122,10 @@
    acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
    acpigen_write_resourcetemplate_footer();

+	/* Define IPC Write Method */
+	if (CONFIG(PMC_IPC_ACPI_INTERFACE))
+		pmc_ipc_acpi_fill_ssdt();
+
    acpigen_pop_len(); /* PMC Device */
    acpigen_pop_len(); /* Scope */