Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50487 )
Change subject: soc/amd/cezanne: select soc-specific ACPI functionality ......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/cezanne/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/50487/comment/6f87695d_997ffd04 PS2, Line 16: uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ : uint8_t lids; /* 0x01 - LID State */ : uint8_t pwrs; /* 0x02 - AC Power State */ : uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ : uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ : uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ : uint8_t tmps; /* 0x17 - Temperature Sensor ID */ : uint8_t tcrt; /* 0x18 - Critical Threshold */ : uint8_t tpsv; /* 0x19 - Passive Threshold */
no, we dont. it's a copy from picasso right now. […]
i've put this on my local todo list for later; i think it would be good to keep cezanne as much aligned to picasso as possible right now. not 100% happy with the unused stuff in here, but keeping it like this will help reducing noise during active development