Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56717 )
Change subject: soc/intel/common: Calculate and configure SF Mask 2 ......................................................................
soc/intel/common: Calculate and configure SF Mask 2
As per TGL EDS, two ways will be controlled with one bit of SF QoS register hence, this patch introduces SF_MASK_2BITS_PER_WAY Kconfig to allow SoC users to select SF_MASK_2BITS_PER_WAY to follow the EDS recommendation.
Calculate SF masks: 1. if CONFIG_SF_MASK_2BITS_PER_WAY: a. data_ways = data_ways / 2
Also, program SF Mask#2 using below logic: 2. Set SF_MASK_2 = (1 << data_ways) - 1
Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 3 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56717/1
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 26f1dcb..9e7e6fd 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -88,6 +88,8 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_SF_QOS_INFO 0xc87 +#define IA32_SF_WAY_COUNT_MASK 0x3f #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 16844d9..77e8429 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -63,6 +63,14 @@ IA32_L3_SF_MASK_x programming is required along with the data ways. This is applicable for TGL and beyond.
+config SF_MASK_2BITS_PER_WAY + bool + depends on INTEL_CAR_NEM_ENHANCED + help + In the case of non-inclusive cache architecture when two ways in + the SF mask is used to control with one bit of SF QoS register. + This is applicable for TGL alone. + config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5f39507..c0814fd 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -508,6 +508,9 @@ */ mov $CONFIG_DCACHE_RAM_SIZE, %eax div %ecx +#if CONFIG(SF_MASK_2BITS_PER_WAY) + mov %eax, %edx /* back up data_ways in edx */ +#endif mov %eax, %ecx movl $0x01, %eax shl %cl, %eax @@ -516,8 +519,30 @@ set_eviction_mask: mov %ebx, %edi /* back up number of ways */ mov %eax, %esi /* back up the non-eviction mask */ +#if CONFIG(SF_MASK_2BITS_PER_WAY) + mov %edx, %ebx /* back up data_ways in ebx */ +#endif #if CONFIG(CAR_HAS_SF_MASKS) /* + * Program MSR 0x1892 Non-Eviction Mask #2 + * IA32_CR_SF_QOS_MASK_2 = ((1 << data_ways) - 1) + */ +#if CONFIG(SF_MASK_2BITS_PER_WAY) + movl $0x01, %ecx + shr %cl, %ebx + mov %ebx, %ecx + movl $0x01, %ebx + shl %cl, %ebx + subl $0x01, %ebx +#else + mov %esi, %ebx +#endif + mov %ebx, %eax /* restore data_ways in eax */ + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_2, %ecx + wrmsr + + /* * SF mask is programmed with the double number of bits than * the number of ways */