[coreboot-gerrit] Change in coreboot[master]: mb/asrock/h110m: enable ACPI LDN in SuperIO

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35370 )

Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO
......................................................................

mb/asrock/h110m: enable ACPI LDN in SuperIO

Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/asrock/h110m/bootblock.c
M src/mainboard/asrock/h110m/devicetree.cb
2 files changed, 14 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35370/1

diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c
index 96ce205..2fa70e1 100644
--- a/src/mainboard/asrock/h110m/bootblock.c
+++ b/src/mainboard/asrock/h110m/bootblock.c
@@ -18,12 +18,25 @@
 #include <soc/gpio.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6791d/nct6791d.h>
+#include <device/pnp_ops.h>
 #include "include/gpio.h"

static void early_config_superio(void)
 {
    const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1);
+	const pnp_devfn_t acpi_dev = PNP_DEV(0x2e, NCT6791D_ACPI);
+
    nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+
+	nuvoton_pnp_enter_conf_state(acpi_dev);
+
+	pnp_set_logical_device(acpi_dev);
+	/* Power RAM in S3 and let the PCH handle power failure actions */
+	pnp_write_config(acpi_dev, 0xe4, 0x70);
+	/* Set Hardware Monitor reset source to LRESET# */
+	pnp_write_config(acpi_dev, 0xe7, 0x01);
+
+	nuvoton_pnp_exit_conf_state(acpi_dev);
 }

static void early_config_gpio(void)
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 8ed3476..038f144 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -365,7 +365,7 @@
    			device pnp 2e.109 off end # GPIO3
    			device pnp 2e.209 off end # GPIO4
    			device pnp 2e.309 off end # GPIO5
-				device pnp 2e.a   off end # ACPI
+				device pnp 2e.a   on  end # ACPI
    			device pnp 2e.b   on      # HWM, LED
    				# HM base address
    				io  0x60 = 0x0290