Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48847 )
Change subject: soc/intel/alderlake: Update CPU microcode patch base address/size ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48847/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48847/1//COMMIT_MSG@9 PS1, Line 9: This patch updates CPU microcode patch base address/size to FSP-S : UPD to have second microcode patch loaded successfully to enable : Mcheck flow
What is "second microcode patch"? […]
on ADL, BIOS should do the second ucode patch load(To Enable MCHECK)
[InitializeMicrocode]: Microcode Region Address = FF41E9D0, Size = 194560 [InitializeMicrocode]: Find a potential patch! LoadMicrocode: Before load, revision = 0x8200000A LoadMicrocode: After load, revision = 0x8200000A ReloadMicrocodePatch: Second patch load success.
without the 2nd microcode loading Mcheck flow won't finished successfuly
https://review.coreboot.org/c/coreboot/+/48847/1/src/soc/intel/alderlake/fsp... File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48847/1/src/soc/intel/alderlake/fsp... PS1, Line 112:
nit: Should there be a additional check whether UCODE is loaded successfully or not?
2nd microcode loading is part of FSP doing MP init process, we are just assigning the UPD.