Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
Yes, if we wanted to advertise memory-mapped TPM support. But isn't it that we […]
this MMIO address range is specific for TPM specification and from Intel PCH side, this address doesn't have anything specific hence we might not need to reserve this range from OS space if required TPM support is not there.
I have verified firmware PCH fixed range list for SPT till latest TGP, this ranges doesn't exist in fixed range as expected.
this is what i have found in TPM ACPI spec
The TPM device is defined with ACPI ID "PNP0C31". Platform builds a SSDT and passes it into the guest through the fw_cfg device. The device description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area.
Earlier all chrome supported IA soc till SPT were using non CR50 TPM hence reserving those range make sense but today with CML and WHL, those address doesn't even valid to reserved in chrome platform