[coreboot-gerrit] Change in coreboot[master]: mb/purism/librem_mini: Adjust GPIO pad config per schematics

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47220 )

Change subject: mb/purism/librem_mini: Adjust GPIO pad config per schematics
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mb/purism/librem_mini: Adjust GPIO pad config per schematics

- set pads GPP_B6/B8 for PCIe CLK_REQ lines
- set pad GPP_B14 to speaker output
- adjust comment for GPP_C22 / USB3_P1_PWREN
- set pad GPP_E4 to NF1 / SATA_DEVSLP0
- set pads GPP_E9/E10 to USB2_OC0#/USB2_OC1#

Change-Id: I8bf8af620370ec2d4c864e513db5d710a9c65d27
Signed-off-by: Matt DeVillier 
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
1 file changed, 13 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/47220/1

diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
index b82dd3a..898b443 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
@@ -99,14 +99,14 @@
    /* GPP_B5 - NC */
    PAD_NC(GPP_B5, NONE),

-	/* GPP_B6 - NC */
-	PAD_NC(GPP_B6, NONE),
+	/* GPP_B6 - SRCCLKREQ1# / SSD_CLK_REQ# */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),

/* GPP_B7 - NC */
    PAD_NC(GPP_B7, NONE),

-	/* GPP_B8 - NC */
-	PAD_NC(GPP_B8, NONE),
+	/* GPP_B8 - SRCCLKREQ3# / LAN2_CLK_REQ# */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),

/* GPP_B9 - NC */
    PAD_NC(GPP_B9, NONE),
@@ -123,8 +123,8 @@
    /* GPP_B13 - PLTRST# */
    PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),

-	/* GPP_B14 - GPIO */
-	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+	/* GPP_B14 - SPKR */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),

/* GPP_B15 - NC */
    PAD_NC(GPP_B15, NONE),
@@ -507,7 +507,7 @@
    /* GPP_C21 - NC */
    PAD_NC(GPP_C21, NONE),

-	/* GPP_C22 - GPIO */
+	/* GPP_C22 - USB3_P1_PWREN */
    PAD_CFG_GPO(GPP_C22, 1, PLTRST),

/* GPP_C23 - NC */
@@ -527,8 +527,8 @@
    /* GPP_E3 - NC */
    PAD_NC(GPP_E3, UP_20K),

-	/* GPP_E4 - GPIO */
-	PAD_CFG_GPO(GPP_E4, 1, PLTRST),
+	/* GPP_E4 - SATA_DEVSLP0 */
+	PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1),

/* GPP_E5 - NC */
    PAD_NC(GPP_E5, UP_20K),
@@ -542,11 +542,11 @@
    /* GPP_E8 - SATALED# */
    PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),

-	/* GPP_E9 - RESERVED */
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5),
+	/* GPP_E9 - USB2_OC0# */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),

-	/* GPP_E10 - RESERVED */
-	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5),
+	/* GPP_E10 - USB2_OC1# */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),

/* GPP_E11 - USB2_OC2# */
    PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),