[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Support to initialize Memory

[Varun Joshi (Code Review)]

Hello Bora Guvendik, build bot (Jenkins), Tim Wawrzynczak, Selma Bensaid, Anil Kumar K, Varun Joshi, Bernardo Perez Priego, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39847

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Support to initialize Memory
......................................................................

soc/intel/tigerlake: Support to initialize Memory

Support to configure DDR4 memory variant which uses SMBus address.
Added support to read SPD data from SMBUS.

BUG=b:151702387

Signed-off-by: Varun Joshi 
Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
M src/soc/intel/tigerlake/meminit_tgl.c
2 files changed, 90 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/39847/5