Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39663 )
Change subject: [WIP] soc/intel/braswell: Clean up ......................................................................
[WIP] soc/intel/braswell: Clean up
Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected.
Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/gpio_support.c M src/soc/intel/braswell/include/soc/gpio.h M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/pcie.c M src/soc/intel/braswell/pmutil.c 13 files changed, 188 insertions(+), 244 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/39663/1
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 2d47663..0221478 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -35,8 +35,8 @@ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), - REG_MSR_RMW(MSR_POWER_MISC, - ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), + REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), + /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), @@ -53,10 +53,9 @@ setup_lapic();
/* - * The turbo disable bit is actually scoped at building - * block level -- not package. For non-bsp cores that are within a - * building block enable turbo. The cores within the BSP's building - * block will just see it already enabled and move on. + * The turbo disable bit is actually scoped at building block level -- not package. + * For non-BSP cores that are within a building block, enable turbo. The cores within + * the BSP's building block will just see it already enabled and move on. */ if (lapicid()) enable_turbo(); @@ -76,9 +75,9 @@ };
static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x406C4 }, - { X86_VENDOR_INTEL, 0x406C3 }, - { X86_VENDOR_INTEL, 0x406C2 }, + { X86_VENDOR_INTEL, 0x406c4 }, + { X86_VENDOR_INTEL, 0x406c3 }, + { X86_VENDOR_INTEL, 0x406c2 }, { 0, 0 }, };
@@ -115,9 +114,8 @@ x86_mtrr_check();
/* - * Configure the BUNIT to allow dirty cache line evictions in non-SMM - * mode for the lines that were dirtied while in SMM mode. Otherwise - * the writes would be silently dropped. + * Configure the BUNIT to allow dirty cache line evictions in non-SMM mode for lines + * that were dirtied while in SMM mode. Otherwise the writes would be silently dropped. */ bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); @@ -190,8 +188,7 @@ intel_microcode_load_unlocked(pattrs->microcode_patch); }
-static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) +static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; @@ -205,22 +202,21 @@ }
static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_southbridge_clear_state, + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = relocation_handler, - .post_mp_init = smm_southbridge_enable_smi, + .relocation_handler = relocation_handler, + .post_mp_init = smm_southbridge_enable_smi, };
void soc_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list;
- printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index b24dff5..1eef5fd 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -51,9 +51,9 @@
static void log_wake_events(const struct chipset_power_state *ps) { - const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | - PCIE_WAKE2_STS | PCIE_WAKE1_STS | - PCIE_WAKE0_STS; + const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS | + PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS; + uint32_t gpe0_sts; uint32_t gpio_mask; int i; diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 23ada25..58a3fef 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -33,8 +33,7 @@ { struct soc_intel_braswell_config *config = config_of(dev);
- printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops);
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 41b2c6f..ff73955 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -32,38 +32,34 @@
static const struct reg_script gfx_post_vbios_script[] = { /* Set Lock bits */ - REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK), + REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK), REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK), REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK), REG_SCRIPT_END };
-static inline void gfx_run_script(struct device *dev, - const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); }
static void gfx_pre_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); }
static void gfx_post_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); }
static void gfx_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
if (!CONFIG(RUN_FSP_GOP)) { /* Pre VBIOS Init */ diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 2ca023f..ebfebae 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -57,39 +57,39 @@
/* GPIO Community descriptions */ static const struct gpio_bank gpnorth_community = { - .gpio_count = GP_NORTH_COUNT, + .gpio_count = GP_NORTH_COUNT, .gpio_to_pad = gpncommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPNORTH_BASE, - .has_gpe_en = GPE_CAPABLE, + .pad_base = COMMUNITY_GPNORTH_BASE, + .has_gpe_en = GPE_CAPABLE, .has_wake_en = 1, };
static const struct gpio_bank gpsoutheast_community = { - .gpio_count = GP_SOUTHEAST_COUNT, + .gpio_count = GP_SOUTHEAST_COUNT, .gpio_to_pad = gpsecommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPSOUTHEAST_BASE, - .has_gpe_en = GPE_CAPABLE_NONE, + .pad_base = COMMUNITY_GPSOUTHEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, .has_wake_en = 1, };
static const struct gpio_bank gpsouthwest_community = { - .gpio_count = GP_SOUTHWEST_COUNT, + .gpio_count = GP_SOUTHWEST_COUNT, .gpio_to_pad = gpswcommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPSOUTHWEST_BASE, - .has_gpe_en = GPE_CAPABLE, + .pad_base = COMMUNITY_GPSOUTHWEST_BASE, + .has_gpe_en = GPE_CAPABLE, .has_wake_en = 1, };
static const struct gpio_bank gpeast_community = { - .gpio_count = GP_EAST_COUNT, + .gpio_count = GP_EAST_COUNT, .gpio_to_pad = gpecommunity_gpio_to_pad, - .pad_base = COMMUNITY_GPEAST_BASE, - .has_gpe_en = GPE_CAPABLE_NONE, + .pad_base = COMMUNITY_GPEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, .has_wake_en = 1, };
static void setup_gpio_route(const struct soc_gpio_map *sw_gpios, - const struct soc_gpio_map *n_gpios) + const struct soc_gpio_map *n_gpios) { const struct soc_gpio_map *n_config; const struct soc_gpio_map *sw_config; @@ -104,82 +104,72 @@ for (sw_config = sw_gpios, n_config = n_gpios; (!north_done || !south_done); sw_config++, n_config++, gpio++) {
- /* when north config is done */ - if ((gpio > GP_NORTH_COUNT) || - (n_config->pad_conf0 == GPIO_LIST_END)) + /* When north config is done */ + if ((gpio > GP_NORTH_COUNT) || (n_config->pad_conf0 == GPIO_LIST_END)) north_done = 1;
/* when sw is done */ - if ((gpio > GP_SOUTHWEST_COUNT) || - (sw_config->pad_conf0 == GPIO_LIST_END)) + if ((gpio > GP_SOUTHWEST_COUNT) || (sw_config->pad_conf0 == GPIO_LIST_END)) south_done = 1;
- /* route north gpios */ + /* Route north gpios */ if (!north_done) { /* Int select from 8 to 15 */ int_selection = ((n_config->pad_conf0 >> 28) & 0xf); + if (n_config->gpe == SMI) { - /* - * Set the corresponding bits (01) as - * per the interrupt line - */ + /* Set the corresponding bits (01) as per the interrupt line */ route_reg |= (1 << ((int_selection - 8) * 2)); - /* reset the higher bit */ - route_reg &= - ~(1 << ((int_selection - 8) * 2 + 1)); - alt_gpio_smi |= (1 << (int_selection + 8)); + + /* Reset the higher bit */ + route_reg &= ~(1 << ((int_selection - 8) * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 8)); + } else if (n_config->gpe == SCI) { - /* - * Set the corresponding bits as per the - * interrupt line - */ - route_reg |= - (1 << (((int_selection - 8) * 2) + 1)); - /* reset the bit */ + /* Set the corresponding bits as per the interrupt line */ + route_reg |= (1 << (((int_selection - 8) * 2) + 1)); + + /* Reset the bit */ route_reg &= ~(1 << ((int_selection - 8) * 2)); - gpe0a_en |= (1 << (int_selection + 8)); + gpe0a_en |= (1 << (int_selection + 8)); } }
- /* route southwest gpios */ + /* Route southwest gpios */ if (!south_done) { /* Int select from 8 to 15 */ int_selection = ((sw_config->pad_conf0 >> 28) & 0xf); + if (sw_config->gpe == SMI) { - /* - * Set the corresponding bits (10) as - * per the interrupt line - */ - route_reg |= (1 << (int_selection * 2)); - route_reg &= ~(1 << (int_selection * 2 + 1)); - alt_gpio_smi |= (1 << (int_selection + 16)); + /* Set the corresponding bits (10) as per the interrupt line */ + route_reg |= (1 << (int_selection * 2)); + route_reg &= ~(1 << (int_selection * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 16)); + } else if (sw_config->gpe == SCI) { - /* - * Set the corresponding bits as - * per the interrupt line - */ + /* Set the corresponding bits as per the interrupt line */ route_reg |= (1 << ((int_selection * 2) + 1)); - /* reset the bit */ + + /* Reset the bit */ route_reg &= ~(1 << (int_selection * 2)); - gpe0a_en |= (1 << (int_selection + 16)); + gpe0a_en |= (1 << (int_selection + 16)); } } }
- /* enable gpe bits in GPE0A_EN_REG */ + /* Enable gpe bits in GPE0A_EN_REG */ outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG);
#ifdef GPIO_DEBUG printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n", route_reg, alt_gpio_smi, gpe0a_en); #endif - /* Save as an smm param */ + /* Save as an SMM param */ smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); }
-static void setup_gpios(const struct soc_gpio_map *gpios, - const struct gpio_bank *community) +static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank *community) { const struct soc_gpio_map *config; int gpio = 0; @@ -191,38 +181,31 @@
if (!gpios) return; - for (config = gpios; config->pad_conf0 != GPIO_LIST_END; - config++, gpio++) { + + for (config = gpios; config->pad_conf0 != GPIO_LIST_END; config++, gpio++) { if (gpio > community->gpio_count) break;
/* Pad configuration registers */ family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO; - internal_pad_num = community->gpio_to_pad[gpio] % - MAX_FAMILY_PAD_GPIO_NO; + internal_pad_num = community->gpio_to_pad[gpio] % MAX_FAMILY_PAD_GPIO_NO;
/* - * Calculate the MMIO Address for specific GPIO pin - * control register pointed by index. - * REG = (IOBASE + COMMUNITY_BASE + (0X04400)) + - * (0X400*FAMILY_NUM) + (8 * PAD_NUM) + * Calculate the MMIO Address for GPIO pin control register pointed by index. + * REG = IOBASE + COMMUNITY_BASE + 0x4400 + (0x400 * FAMILY_NUM) + (8 * PAD_NUM) */ - mmio_addr = FAMILY_PAD_REGS_OFF - + (FAMILY_PAD_REGS_SIZE * family) - + (GPIO_REGS_SIZE * internal_pad_num); + mmio_addr = FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * family) + + (GPIO_REGS_SIZE * internal_pad_num);
reg = community->pad_base + mmio_addr;
- /* get int selection value */ + /* Get int selection value */ int_selection = ((config->pad_conf0 >> 28) & 0xf);
- /* get int mask register value */ + /* Get int mask register value */ gpio_int_mask |= (config->int_mask << int_selection);
- /* - * wake capable programming - * some communities have 2 wake regs - */ + /* Wake capable programming, some communities have 2 wake regs */ if (gpio > 31) gpio_wake1 |= config->wake_mask << (gpio % 32); else @@ -235,50 +218,38 @@ reg, config->pad_conf0, config->pad_conf1, community->gpio_to_pad[gpio], gpio); #endif - /* - * write pad configurations to conf0 and conf1 register - */ - write32((void *)(reg + PAD_CONF0_REG), - config->pad_conf0); - write32((void *)(reg + PAD_CONF1_REG), - config->pad_conf1); + /* Write pad configurations to conf0 and conf1 register */ + write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0); + write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1); } }
#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, - "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n", + printk(BIOS_DEBUG, "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n", gpio_wake0, gpio_wake1, gpio_int_mask); #endif
/* Wake */ - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), - gpio_wake0); + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0);
- /* wake mask config for communities with 2 regs */ + /* Wake mask config for communities with 2 regs */ if (community->gpio_count > 32) - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), - gpio_wake1); + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1);
/* Interrupt */ - write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), - gpio_int_mask); - + write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); }
void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) { - if (config) {
/* - * Write the default value 0xffffff to the SW - * write_access_policy_interrupt_reg to allow the SW interrupt - * mask register to be set + * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg + * to allow the SW interrupt mask register to be set */ - write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), - 0xffffffff); + write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff);
printk(BIOS_DEBUG, "north\n"); setup_gpios(config->north, &gpnorth_community); @@ -297,8 +268,8 @@ }
/* - * Set on die termination feature with pull up value and - * drive the pad high for TAP_TDO and TAP_TMS + * Set on die termination feature with pull up value + * and drive the pad high for TAP_TDO and TAP_TMS */ if (!enable_xdp_tap) printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c index 7dccc7b..d2abccc 100644 --- a/src/soc/intel/braswell/gpio_support.c +++ b/src/soc/intel/braswell/gpio_support.c @@ -24,10 +24,9 @@ uint16_t gpio_family_number(uint8_t community, uint8_t pad) { /* - * Refer to BSW BIOS Writers Guide, Table "Family Number". - * BSW has 4 GPIO communities. Each community has up to 7 families and - * each family contains a range of Pad numbers. The number in the array - * is the maximum no. of that range. + * Refer to BSW BIOS Writers Guide, Table "Family Number". BSW has 4 GPIO communities. + * Each community has up to 7 families and each family contains a range of Pad numbers. + * The number in the array is the maximum no. of that range. * For example: East community, family 0, Pad 0~11. */ static const uint8_t community_base[GPIO_COMMUNITY_COUNT] @@ -57,8 +56,7 @@ }
/* - * Return pad configuration register offset by pad number and which community - * it is in. + * Return pad configuration register offset by pad number and which community it is in. */ uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad) { @@ -69,12 +67,11 @@ fpad = gpio_family_number(community, pad);
/* - * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space - * Registers Addresses" for the Pad configuration register calculation. + * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space Registers Addresses" + * for the Pad configuration register calculation. */ - pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) - + FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * (fpad >> 8)) - + (GPIO_REGS_SIZE * (fpad & 0xff))); + pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + FAMILY_PAD_REGS_OFF + + (FAMILY_PAD_REGS_SIZE * (fpad >> 8)) + (GPIO_REGS_SIZE * (fpad & 0xff)));
return pad_config_reg; } @@ -86,17 +83,18 @@ if (gpio_num >= GP_SW_00 && gpio_num <= GP_SW_97) { comm = GP_SOUTHWEST; *pad = gpio_num % GP_SOUTHWEST_COUNT; + } else if (gpio_num >= GP_NC_00 && gpio_num <= GP_NC_72) { comm = GP_NORTH; *pad = gpio_num % GP_SOUTHWEST_COUNT; + } else if (gpio_num >= GP_E_00 && gpio_num <= GP_E_26) { comm = GP_EAST; - *pad = gpio_num % - (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT); + *pad = gpio_num % (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT); + } else { comm = GP_SOUTHEAST; - *pad = gpio_num % (GP_SOUTHWEST_COUNT + - GP_NORTH_COUNT + GP_EAST_COUNT); + *pad = gpio_num % (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT); } return comm; } @@ -107,10 +105,8 @@ int pad_num = 0; uint32_t *pad_config0_reg; uint32_t *pad_config1_reg; - int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT - + GP_SOUTHEAST_COUNT;
- if (gpio_num > max_gpio_cnt) + if (gpio_num > MAX_GPIO_CNT) return; /* Get GPIO Community based on GPIO_NUMBER */ comm = gpio_get_community_num(gpio_num, &pad_num); @@ -147,10 +143,8 @@ int pad_num = 0; uint32_t *pad_config0_reg; u32 pad_value; - int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT - + GP_SOUTHEAST_COUNT;
- if (gpio_num > max_gpio_cnt) + if (gpio_num > MAX_GPIO_CNT) return -1;
/* Get GPIO Community based on GPIO_NUMBER */ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 51c8e12..e40a951 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -133,6 +133,8 @@ #define GP_EAST_COUNT 24 #define GP_SOUTHEAST_COUNT 55
+#define MAX_GPIO_CNT (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT + GP_SOUTHEAST_COUNT) + /* General */ #define GPIO_REGS_SIZE 8 #define NA 0 diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index bf58074..8b7c1ea 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -50,48 +50,47 @@ static void lpc_gpio_config(u32 cycle) { if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_FRAME_MMIO_OFFSET), + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD0_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD1_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD2_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD3_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_CLKRUN_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_PD20K(1)); + } else { /* Resume cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_FRAME_MMIO_OFFSET), + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD0_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD1_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD2_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_AD3_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + - LPC_CLKRUN_MMIO_OFFSET), + + write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); } }
/* - * configure LPC GPIO lines for low power + * Configure LPC GPIO lines for low power */ void lpc_set_low_power(void) { diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 12d2858..85e698c 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -31,7 +31,6 @@ #include <soc/ramstage.h> #include "chip.h"
- /* * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB * address. Just take 1MiB @ 512MiB. @@ -58,12 +57,12 @@ static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - | PCI_COMMAND_INT_DISABLE), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), + /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, - LPE_PCICFGCTR1_PCI_CFG_DIS | - LPE_PCICFGCTR1_ACPI_INT_EN), + LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN), + REG_SCRIPT_END }; global_nvs_t *gnvs; @@ -101,11 +100,13 @@ freq_str = "19.2MHz External Crystal"; reg = CLK_SRC_XTAL; break; + case LPE_CLK_SRC_PLL: /* PLL driven bit2=1 */ freq_str = "19.2MHz PLL"; reg = CLK_SRC_PLL; break; + default: reg = CLK_SRC_XTAL; printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); @@ -118,7 +119,7 @@
printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
- clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); + clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } @@ -136,15 +137,13 @@ printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base);
/* Continue using old way of informing firmware address / size. */ - pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
/* Also put the address in MMIO space like on C0 BTM */ mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), - res->base); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), - res->size); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); }
@@ -152,8 +151,7 @@ { struct soc_intel_braswell_config *config = config_of(dev);
- printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
lpe_stash_firmware_info(dev); setup_codec_clock(dev); @@ -168,7 +166,7 @@ pci_dev_read_resources(dev);
/* - * Allocate the BAR1 resource at index 2 to fulfil the Windows driver + * Allocate the BAR1 resource at index 2 to fulfill the Windows driver * interface requirements even though the PCI device has only one BAR */ res = new_resource(dev, PCI_BASE_ADDRESS_2); @@ -179,8 +177,7 @@ res->align = 12; res->flags = IORESOURCE_MEM;
- reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, - FIRMWARE_PHYS_BASE >> 10, + reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10, FIRMWARE_PHYS_LENGTH >> 10); }
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 6bc4065..b5c4e3d 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -27,16 +27,15 @@
#include "chip.h"
-static void dev_enable_acpi_mode(struct device *dev, - int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END }; struct resource *bar; @@ -65,10 +64,6 @@ reg_script_run_on_dev(dev, ops); }
-static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) -{ - *iosf_reg = -1; - *nvs_index = -1; #define SET_IOSF_REG(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ do { \ @@ -76,6 +71,11 @@ *nvs_index = LPSS_NVS_ ## name_; \ } while (0)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) +{ + *iosf_reg = -1; + *nvs_index = -1; + switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); break; @@ -108,6 +108,8 @@ } }
+#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ @@ -116,9 +118,6 @@ REG_SCRIPT_END, };
-#define CASE_I2C(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - switch (dev->path.pci.devfn) { CASE_I2C(I2C1) : CASE_I2C(I2C2) : @@ -140,19 +139,15 @@ struct soc_intel_braswell_config *config = config_of(dev); int iosf_reg, nvs_index;
- printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); - printk(BIOS_SPEW, "%s - %s\n", - get_pci_class_name(dev), - get_pci_subclass_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s - %s\n", get_pci_class_name(dev), get_pci_subclass_name(dev));
dev_ctl_reg(dev, &iosf_reg, &nvs_index);
if (iosf_reg < 0) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func); return; }
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 04e5d7b..28b9e0e 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -19,7 +19,7 @@ static size_t smm_region_size(void) { u32 smm_size; - smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF; + smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF; smm_size -= iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF; smm_size = (smm_size + 1) << 20; return smm_size; diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 7ab184f..4745be9 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -40,8 +40,7 @@
static void pcie_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); }
static const struct reg_script no_dev_behind_port[] = { @@ -86,14 +85,12 @@ static struct device *port1_dev;
/* - * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. - * For each port initial assumption is that, each port will have - * devices connected to it. Later we will scan each PORT and if - * the device is not attached to that port we will update - * rootports_in_use. If none of the root port is in use we will - * disable PORT1 otherwise we will keep PORT1 enabled per spec. - * In future if the Soc has more number of PCIe Root ports then - * change MAX_ROOT_PORTS_BSW value accordingly. + * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. For each port initial + * assumption is that, each port will have devices connected to it. Later we will + * scan each PORT and if the device is not attached to that port we will update + * rootports_in_use. If none of the root port is in use we will disable PORT1 + * otherwise we will keep PORT1 enabled per spec. In future if the SoC has more + * number of PCIe Root ports then change MAX_ROOT_PORTS_BSW value accordingly. */
static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; @@ -109,9 +106,9 @@ printk(BIOS_DEBUG, "No PCIe device present.");
/* - * Defer PORT1 disabling for now. When we are at Last port - * we will check rootports_in_use and disable PORT1 if none - * of the port has any device connected + * Defer PORT1 disabling for now. When we are at Last port we will check + * rootports_in_use and disable PORT1 if none of the ports have any device + * connected to it. */ if (!is_first_port(dev)) { reg_script_run_on_dev(dev, no_dev_behind_port); @@ -119,8 +116,8 @@ } else port1_dev = dev; /* - * If none of the ROOT PORT has devices connected then - * disable PORT1 else keep the PORT1 enable + * If none of the ROOT PORT has devices connected then disable PORT1. + * Else, keep the PORT1 enabled. */ if (!rootports_in_use) { reg_script_run_on_dev(port1_dev, no_dev_behind_port); @@ -136,8 +133,8 @@
static void pcie_enable(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + if (is_first_port(dev)) { struct soc_intel_braswell_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); @@ -146,8 +143,7 @@ strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
if (config->pcie_wake_enable) - smm_southcluster_save_param( - SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); + smm_southcluster_save_param(SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); }
/* Check if device is enabled in strapping. */ diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index f218259..9c5079f 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -53,8 +53,7 @@ return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; }
-static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) +static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) { int i;
@@ -310,16 +309,16 @@ { uint32_t alt_gpio_sts; static const char *const alt_gpio_smi_sts_bits[] = { - [0] = "SUS_GPIO_0", - [1] = "SUS_GPIO_1", - [2] = "SUS_GPIO_2", - [3] = "SUS_GPIO_3", - [4] = "SUS_GPIO_4", - [5] = "SUS_GPIO_5", - [6] = "SUS_GPIO_6", - [7] = "SUS_GPIO_7", - [8] = "CORE_GPIO_0", - [9] = "CORE_GPIO_1", + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", [10] = "CORE_GPIO_2", [11] = "CORE_GPIO_3", [12] = "CORE_GPIO_4",