build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35348 )
Change subject: Rangeley: Fix incorrect BCLK
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35348/1/src/cpu/intel/fsp_model_406...
File src/cpu/intel/fsp_model_406dx/acpi.c:
https://review.coreboot.org/c/coreboot/+/35348/1/src/cpu/intel/fsp_model_406...
PS1, Line 175: printk(BIOS_DEBUG,"MSR_PSB_CLOCK_STS %x:%x BCLK:%dHz ratio:%d\n",
space required after that ',' (ctx:VxV)
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f
Gerrit-Change-Number: 35348
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Gerrit-Reviewer: David Guckian
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Gerrit-Reviewer: Patrick Rudolph
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Gerrit-Reviewer: hannah.williams@dell.com
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Gerrit-Comment-Date: Wed, 11 Sep 2019 19:10:39 +0000
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