Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@23 PS2, Line 23: to avoid conflicts with current mainboard builds.
Please argue why everything has to be split, and why no common code between the two can exist?
Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE}
GPIO: GPIO communities have their own differences. This requires conditional checks in gpio.asl, gpio.c, gpio*.h, pmc.h and gpio.asl
PCI IRQs: Set up differently for JSL and TGL
PCIe: Number of Root ports differ.
eMMC/SD: Only supported on JSL.
XHCI Different for JSL and TGL.
Memory configuration are different for JSL and TGL
FSP params for JSL, FSP params for TGL are different.
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@22 PS2, Line 22: 1. Copy Tiger Lake SoC code as is, and change SoC Kconfig : to avoid conflicts with current mainboard builds. : : 2. Clean up TGL code out of copy patch done in step 1. : Make it JSL only code. The SoC config still kept as : SOC_INTEL_JASPERLAKE_COPY. : : 3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to : SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can : bind to SoC code from soc/intel/jasperlake. This step establishes : Jasper Lake as a separate SoC. : : 4. Clean up current JSL code from TGL code. This step establishes Tiger : Lake as a separate SoC.
Please re-flow for 72/75 characters per line.
Done