22 Oct
2019
22 Oct
'19
6:17 a.m.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )
Change subject: Add configurable ramstage support for minimal PCI scanning ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36221/3/util/sconfig/lex.yy.c_shipp... File util/sconfig/lex.yy.c_shipped:
https://review.coreboot.org/c/coreboot/+/36221/3/util/sconfig/lex.yy.c_shipp... PS3, Line 162: is this valid or existing junk whitespace ?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Gerrit-Change-Number: 36221
Gerrit-PatchSet: 3
Gerrit-Owner: ron minnich rminnich@gmail.com
Gerrit-Reviewer: Jeremy Soller jeremy@system76.com
Gerrit-Reviewer: Lean Sheng Tan lean.sheng.tan@intel.com
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
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Gerrit-Comment-Date: Tue, 22 Oct 2019 06:17:58 +0000
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