[coreboot-gerrit] Change in coreboot[master]: hatch: Fix FPMCU pwr/rst gpio handling

[Craig Hesling (Code Review)]

Craig Hesling has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37459 )

Change subject: hatch: Fix FPMCU pwr/rst gpio handling
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37459/2/src/mainboard/google/hatch/... 
File src/mainboard/google/hatch/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/37459/2/src/mainboard/google/hatch/... 
PS2, Line 414: 1
> It looks like it points back to b/128686027, but it is unclear if this particular change fixed the b […]

Ahh, okay. I think I understand what https://review.coreboot.org/c/coreboot/+/32111 is doing now.

The concern is if user space configures the GPP_A12 to it's native3 function and the system enters s3 or s5. This could result in bad behavior.

Okay, I will ensure that this pin is set to output in either case.