[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0

[Rex-BC Chen (Code Review)]

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62563 )

Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0
......................................................................

soc/mediatek/mt8186: Modify internal capid to 0xE0

Request from Google hardware team:
We cannot disable the internal cap. Therefore, set 0xE0 for all
boards to minimize the internal cap. And it's allowed for ODM to
choose xtal with higher cload if the frequency requirement meets,
and ODM can tune the total capacitance externally.

BUG=b:218439447
TEST=set capid to 0xe0.

Signed-off-by: Rex-BC Chen 
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
---
M src/soc/mediatek/mt8186/rtc.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62563/1

diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c
index 2f78be8..7375bc3 100644
--- a/src/soc/mediatek/mt8186/rtc.c
+++ b/src/soc/mediatek/mt8186/rtc.c
@@ -13,7 +13,7 @@
 #include <soc/pmic_wrap.h>
 #include <timer.h>

-#define MT8186_RTC_DXCO_CAPID 0xC0
+#define MT8186_RTC_DXCO_CAPID 0xE0

/* Initialize RTC setting of using DCXO clock */
 static bool rtc_enable_dcxo(void)