Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24986
Change subject: soc/intel/braswell: increase LPEA fw allocation to 2MiB ......................................................................
soc/intel/braswell: increase LPEA fw allocation to 2MiB
Increase memory allocated for the LPEA firmware from 1MiB to 2MiB to match Intel CHT reference code and fix Windows functionality.
Test: boot Windows on google/edgar, observe no error in Device Manager for LPEA audio device due to BAR2 resource allocation.
Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/soc/intel/braswell/acpi/lpe.asl M src/soc/intel/braswell/lpe.c 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/24986/1
diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index 6dd73ab..145e608 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -26,7 +26,7 @@ { Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) - Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) + Memory32Fixed (ReadWrite, 0, 0x00200000, BAR2) Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) { LPE_DMA0_IRQ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 58b5a8d..8ec944b 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -38,7 +38,7 @@ * address. Just take 1MiB @ 512MiB. */ #define FIRMWARE_PHYS_BASE (512 << 20) -#define FIRMWARE_PHYS_LENGTH (1 << 20) +#define FIRMWARE_PHYS_LENGTH (2 << 20) #define FIRMWARE_PCI_REG_BASE 0xa8 #define FIRMWARE_PCI_REG_LENGTH 0xac #define FIRMWARE_REG_BASE_C0 0x144000