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Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#52).
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
5 files changed, 147 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/52
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Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
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