Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31949
Change subject: Doc/mb/asrock/h110m: update info about PEG ......................................................................
Doc/mb/asrock/h110m: update info about PEG
- Now there is no need to additionally configure the FSP before building; - PEG works with high link speed 8 GT/s (Gen 3); - external GPU supported, but dynamic switching between iGPU and PEG is not yet supported.
Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M Documentation/mainboard/asrock/h110m-dvs.md 1 file changed, 6 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/1
diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 7bc38ff..c9be798 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -23,22 +23,10 @@
Please take FSP from the directory `3rdparty/fsp/KabylakeFspBinPkg/` in the coreboot or download the latest version from [github][FSP github]. - -You must use [Intel Binary Configuration Tool] BCT to set the following -parameters in FSP.fd to initialize the PEG x16 port: - -```eval_rst - Peg0Enable = Enable - Peg0MaxLinkSpeed = Gen3 - Peg0MaxLinkWidth = Auto -``` - -BCT creates Fsp_M.fd, Fsp_S.fd and Fsp_T.fd. These files are integrated -into the coreboot image. If PEG port is not used, you can get these files -without BTC: +You must prepare the FSP for integration into the coreboot image:
```bash -# split FSP.fd +# split FSP.fd: Fsp_M.fd and Fsp_S.fd should be used in building the image python 3rdparty/fsp/Tools/SplitFspBin.py split -f 3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd ```
@@ -97,10 +85,9 @@
## Known issues
-- The VGA port doesn't work. - -- PEG x16 port training correctly runs only at link speed of 2.5GT/s(gen1). - It takes more time to research the schematic of this board. +- The VGA port doesn't work. Discrete graphic card is used as primary + device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not + set). Dynamic switching between iGPU and PEG is not yet supported.
- SuperIO GPIO pin is used to reset Realtek chip. However, since the Logical Device 7 (GPIO6, GPIO7, GPIO8) is not initialized, the network @@ -121,7 +108,7 @@
- integrated graphics init with libgfxinit (see [Known issues](#known-issues)) - PCIe x1 -- PEG x16 Gen1 (see [Known issues](#known-issues)) +- PEG x16 Gen3 - SATA - USB - serial port @@ -131,7 +118,6 @@
## TODO
-- PEG x16 Gen3 - NCT6791D GPIOs - onboard network (see [Known issues](#known-issues)) - S3 suspend/resume @@ -156,7 +142,6 @@
[ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ [FSP github]: https://github.com/IntelFsp/FSP -[Intel Binary Configuration Tool]: https://github.com/IntelFsp/BCT [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2... [flashrom]: https://flashrom.org/Flashrom [H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf