Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Shamile Khan, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph, Prashant Malani, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42295
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Update TCSS for SW CM support ......................................................................
soc/intel/tigerlake: Update TCSS for SW CM support
This change adds support for SW CM. Add Operating System Capabilities (_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet Protocol tunneling and enable PCIe tunneling as well. Remove Connect Topology(CNTP) command because kernel driver directly works with SW CM Thunderbolt firmware. Update _DSD method for USB4 support across XHCI and PCIe root ports.
BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74 --- M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/acpi/tcss_xhci.asl 4 files changed, 217 insertions(+), 220 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42295/6