[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related variables

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45077 )

Change subject: soc/intel/elkhartlake: Update SA & PM related variables
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soc/intel/elkhartlake: Update SA & PM related variables

1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng 
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
---
M src/soc/intel/elkhartlake/include/soc/iomap.h
M src/soc/intel/elkhartlake/include/soc/pm.h
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45077/1

diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h
index 5ba40bc..0246673 100644
--- a/src/soc/intel/elkhartlake/include/soc/iomap.h
+++ b/src/soc/intel/elkhartlake/include/soc/iomap.h
@@ -47,8 +47,8 @@
 #define VTD_BASE_ADDRESS	0xfed90000
 #define VTD_BASE_SIZE		0x00004000

-#define MCH_BASE_ADDRESS	0xfea80000
-#define MCH_BASE_SIZE		0x8000
+#define MCH_BASE_ADDRESS	0xfec80000
+#define MCH_BASE_SIZE		0x80000

#define EARLY_GSPI_BASE_ADDRESS	0xfe011000

diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h
index 11d6663..6ebbbfa 100644
--- a/src/soc/intel/elkhartlake/include/soc/pm.h
+++ b/src/soc/intel/elkhartlake/include/soc/pm.h
@@ -65,7 +65,7 @@
 #define  SMI_ON_SLP_EN_STS_BIT		4
 #define  LEGACY_USB_STS_BIT		3
 #define  BIOS_STS_BIT			2
-#define GPE_CNTL		0x42
+#define GPE_CNTL		0x40
 #define  SWGPE_CTRL		(1 << 1)
 #define DEVACT_STS		0x44
 #define PM2_CNT			0x50