[coreboot-gerrit] Change in coreboot[master]: util/amdfwtool: Fix EFS generation polarity

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47769 )

Change subject: util/amdfwtool: Fix EFS generation polarity
......................................................................

util/amdfwtool: Fix EFS generation polarity

The DWORD used to indicate the Embedded Firmware Structure's generation
uses 1 to indicate a first-gen structure, e.g. a SPI device's erased
value of 0xffffffff.  A 0 in bit 0 is how Client PSPs will interpret
the structure as designed for second-gen.

This change and the original addition should have no effects on
any current products as none interpret offset 0x24.

BUG=b:158755102
TEST=inspect EFS in coreboot.rom

Signed-off-by: Marshall Dawson 
Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd
---
M util/amdfwtool/amdfwtool.c
1 file changed, 2 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47769/1

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 9cf6a4f..36d669b 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -333,7 +333,7 @@
    uint32_t bios0_entry; /* todo: add way to select correct entry */
    uint32_t bios1_entry;
    uint32_t bios2_entry;
-	uint32_t second_gen_efs;
+	uint32_t second_gen_efs; /* Client SKUs b0=1 is Gen1, b1=0 is Gen2, Servers TBD */
    uint32_t bios3_entry;
    uint32_t reserved_2Ch;
    uint32_t promontory_fw_ptr;
@@ -1182,13 +1182,11 @@
    }
    switch (soc_id) {
    case PLATFORM_STONEYRIDGE:
-		amd_romsig->second_gen_efs = 0;
    	amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode;
    	amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed;
    	break;
    case PLATFORM_RAVEN:
    case PLATFORM_PICASSO:
-		amd_romsig->second_gen_efs = 0;
    	amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode;
    	amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed;
    	switch (efs_spi_micron_flag) {
@@ -1205,7 +1203,7 @@
    	break;
    case PLATFORM_RENOIR:
    case PLATFORM_LUCIENNE:
-		amd_romsig->second_gen_efs = 1;
+		amd_romsig->second_gen_efs = 0xfffffffe;
    	amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode;
    	amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed;
    	switch (efs_spi_micron_flag) {