[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )

Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44205/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44205/2//COMMIT_MSG@11 
PS2, Line 11: along with PCI_COMMAND_MEMORY (BIT 1).
Is that required by some specification?