Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33421 )
Change subject: util/superiotool/nuvoton.c: add NCT5539D register dump ......................................................................
Patch Set 10:
(9 comments)
https://review.coreboot.org/#/c/33421/9/util/superiotool/nuvoton.c File util/superiotool/nuvoton.c:
https://review.coreboot.org/#/c/33421/9/util/superiotool/nuvoton.c@637 PS9, Line 637: 0xa0
from the superiotool output 0xa0 seems to be the correct value
The datasheet says something about this register:
Attribute: R/W; Power well: VRTC; Reset by: Battery reset. Default: a0h
Bits 7-2 are reserved. Bit 1 is Deep S3 Enable. Bit 0 is Deep S5 Enable.
The default value of 'a0h' is rather weird. It's also the one using an hex digit in lowercase. Noteworthy.
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c File util/superiotool/nuvoton.c:
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@611 PS10, Line 611: 0x00 NANA
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@611 PS10, Line 611: 0x00 NANA
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@611 PS10, Line 611: 0x00 NANA
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@611 PS10, Line 611: 0x00 NANA
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@612 PS10, Line 612: 0x00 NANA
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@612 PS10, Line 612: 0x00 NANA
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@612 PS10, Line 612: 0x00 NANA
https://review.coreboot.org/#/c/33421/10/util/superiotool/nuvoton.c@638 PS10, Line 638: Maximun Duty Cycle Value Please remove, it is specific to CR 0xf0