Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64426 )
Change subject: driver/intel/fsp2_0: Disable NULL deref code on some FSP ......................................................................
driver/intel/fsp2_0: Disable NULL deref code on some FSP
Some FSP releases dereference NULL and need this workaround.
Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/include/arch/null_breakpoint.h M src/arch/x86/null_breakpoint.c M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/cannonlake/Kconfig 5 files changed, 31 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/64426/1
diff --git a/src/arch/x86/include/arch/null_breakpoint.h b/src/arch/x86/include/arch/null_breakpoint.h index bc86dc0..9d69d3c 100644 --- a/src/arch/x86/include/arch/null_breakpoint.h +++ b/src/arch/x86/include/arch/null_breakpoint.h @@ -7,10 +7,15 @@
/* Places data and instructions breakpoints at address zero. */ void null_breakpoint_init(void); +void null_breakpoint_disable(void); #else static inline void null_breakpoint_init(void) { - /* Not implemented */ + /* Not implemented */ +} +static inline void null_breakpoint_disable(void) +{ + /* Not implemented */ } #endif #endif /* _NULL_BREAKPOINT_H_ */ diff --git a/src/arch/x86/null_breakpoint.c b/src/arch/x86/null_breakpoint.c index dbb54ae..f4b7969 100644 --- a/src/arch/x86/null_breakpoint.c +++ b/src/arch/x86/null_breakpoint.c @@ -57,11 +57,16 @@ create_instruction_breakpoint(); }
-static void null_breakpoint_disable(void *unused) +void null_breakpoint_disable(void) { breakpoint_remove(null_fetch_bp); breakpoint_remove(null_deref_bp); }
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_disable, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_disable, NULL); +static void null_breakpoint_disable_hook(void *unused) +{ + null_breakpoint_disable(); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL); diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8c36063..3a62a92 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -381,4 +381,10 @@ coreboot native debug driver when coreboot has integrated the debug FSP binaries. coreboot disables serial messages when this config is not enabled.
+config FSP_ACESSES_NULL_WORKAROUND + bool + depends on DEBUG_HW_BREAKPOINTS + help + Select this on FSP releases that do acces address '0'. + endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 4f95462..c3ed348 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <security/vboot/antirollback.h> +#include <arch/null_breakpoint.h> #include <arch/symbols.h> #include <assert.h> #include <cbfs.h> @@ -11,17 +11,18 @@ #include <fsp/api.h> #include <fsp/util.h> #include <memrange.h> +#include <mode_switch.h> #include <mrc_cache.h> #include <program_loading.h> #include <romstage_handoff.h> +#include <security/tpm/tspi.h> +#include <security/vboot/antirollback.h> +#include <security/vboot/vboot_common.h> #include <string.h> #include <symbols.h> #include <timestamp.h> -#include <security/vboot/vboot_common.h> -#include <security/tpm/tspi.h> -#include <vb2_api.h> #include <types.h> -#include <mode_switch.h> +#include <vb2_api.h>
static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
@@ -293,6 +294,8 @@ fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
+ if (CONFIG(FSP_ACESSES_NULL_WORKAROUND)) + null_breakpoint_disable(); post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) @@ -301,6 +304,8 @@ (uintptr_t)fsp_get_hob_list_ptr()); else status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); + if (CONFIG(FSP_ACCESSES_NULL_WORKAROUND)) + null_breakpoint_init();
post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7c317e9..d7d1687 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -9,6 +9,7 @@ select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select FSP_ACESSES_NULL_WORKAROUND
config SOC_INTEL_WHISKEYLAKE bool