[coreboot-gerrit] [S] Change in coreboot[main]: mb/google/brya/var/trulo: Add TCSS port descriptions

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83548?usp=email )

Change subject: mb/google/brya/var/trulo: Add TCSS port descriptions
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mb/google/brya/var/trulo: Add TCSS port descriptions

This patch adds descriptions for TCSS port, including over-current
(OC) pin configuration, to the device tree.

It also includes entries that will generate ACPI code at runtime
with port definitions, locations, and type information.

Additionally, implement the TCSS PMC MUX programming.

BUG=b:351976770
TEST=Builds successfully for google/trulo.

Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 32 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 56d96ff..03f7f9e 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -17,8 +17,28 @@
    register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0 (MLB)
    register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A1 (DB)

+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
+	# Bit 2 - C1 has a redriver which does SBU muxing.
+	# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
+	register "tcss_aux_ori" = "0"
+
    device domain 0 on
    	device ref igpu on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
    	device ref xhci on
    		chip drivers/usb/acpi
    			device ref xhci_root_hub on
@@ -84,8 +104,20 @@
    	device ref ufs on end
    	device ref pch_espi on
    		chip ec/google/chromeec
+				use conn0 as mux_conn[0]
    			device pnp 0c09.0 on end
    		end
    	end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port5 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
    end
 end