Attention is currently required from: Martin L Roth.
Hello Martin L Roth,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/81543?usp=email
to review the following change.
Change subject: Update opensbi submodule to upstream master branch ......................................................................
Update opensbi submodule to upstream master branch
Updating from commit id 5019fd124b4c (2022-09-01): include: sbi: Reduce includes in sbi_pmu.h
to commit id 5186da687deb (2024-03-20): platform: generic: allwinner: sun20i-d1: Remove duplicated CSR definitions
This brings in 465 new commits.
Tested on the SiFive unmatched.
Change-Id: I50ce0ba3b6409247a94b49565cc04454903e88d0 Signed-off-by: Martin Roth gaumless@gmail.com Signed-off-by: Ronald G Minnich rminnich@gmail.com --- M 3rdparty/opensbi M src/arch/riscv/opensbi.c M src/soc/sifive/fu540/memlayout.ld M src/soc/sifive/fu740/memlayout.ld 4 files changed, 9 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81543/1
diff --git a/3rdparty/opensbi b/3rdparty/opensbi index 5019fd1..5186da6 160000 --- a/3rdparty/opensbi +++ b/3rdparty/opensbi @@ -1 +1 @@ -Subproject commit 5019fd124b4c46e1581129c5154fc2cdd3b777ed +Subproject commit 5186da687debaab5c4a81ec351e56d145d88c79c diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index bf26b22..9409f0d 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -4,6 +4,7 @@ #undef __packed #undef __noreturn #undef __aligned +#undef __always_inline
#include <sbi/fw_dynamic.h> #include <arch/boot.h> diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index 8fc875d..404e009 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -21,8 +21,8 @@ L2LIM_END(FU540_L2LIM + 2M)
DRAM_START(FU540_DRAM) - REGION(opensbi, FU540_DRAM, 128K, 4K) - RAMSTAGE(FU540_DRAM + 128K, 2M) - MEM_STACK(FU540_DRAM + 128K + 2M, 20K) + OPENSBI(FU540_DRAM, 512K) + RAMSTAGE(FU540_DRAM + 512K, 2M) + MEM_STACK(FU540_DRAM + 768K + 2M, 20K) POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M) } diff --git a/src/soc/sifive/fu740/memlayout.ld b/src/soc/sifive/fu740/memlayout.ld index 85d2b40..e69a9e7d 100644 --- a/src/soc/sifive/fu740/memlayout.ld +++ b/src/soc/sifive/fu740/memlayout.ld @@ -18,9 +18,9 @@ SRAM_END(FU740_L2LIM + 2M)
DRAM_START(FU740_DRAM) - OPENSBI(FU740_DRAM, 256K) + OPENSBI(FU740_DRAM, 512K) /* The 256K size is not allocated. It's just for basic size checking. */ - RAMSTAGE(FU740_DRAM + 256K, 256K) - MEM_STACK(FU740_DRAM + 512K, 20K) - POSTRAM_CBFS_CACHE(FU740_DRAM + 532K, 32M - 532K) + RAMSTAGE(FU740_DRAM + 512K, 256K) + MEM_STACK(FU740_DRAM + 768K, 20K) + POSTRAM_CBFS_CACHE(FU740_DRAM + 788K, 32M - 788K) }