Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: Correct PCIe ports setting for mushu ......................................................................
Patch Set 8:
(8 comments)
Patch Set 8:
Still wondering about my question in patch set #5 below?
Line 80: Sorry, updating the last comment. Is PCIe port 3 being used for testing at the moment? if that's the case, then can we not commit the changes for now? This is not consistent with the current schematics.
I have changed from PCIe port 3 to PCIe port 8 in patch set #8. But this is just reserved and not being used at the moment. I will remove it in next patch.
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@7 PS6, Line 7: mb/google/hatch: modify PCIe ports setting for mushu
mb/google/hatch/var/mushu: Correct PCIe port configuration
Done
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@9 PS6, Line 9: Enabled
Enable
Done
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@10 PS6, Line 10: prot
port
Done
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@11 PS6, Line 11: Enabled
Enable
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: # Enable Root port 13(x4) for dGPU.
Please remove the dot at the end.
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: 13(x4)
Please add a space before (.
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 75: # PCIe port 8 reserve for GPU REFCLK
… reserve*d* for …
Done
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 87: register "PcieClkSrcClkReq[3]" = "3"
I agree. […]
Done