[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43181 )

Change subject: soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND
......................................................................

soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND

The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops.

Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181
Tested-by: build bot (Jenkins) 
Reviewed-by: Frans Hendriks 
Reviewed-by: Wim Vervoorn 
---
M src/soc/intel/braswell/lpss.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Wim Vervoorn: Looks good to me, approved
  Frans Hendriks: Looks good to me, approved

diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index d9027f5..323d406 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -19,7 +19,7 @@
 {
    struct reg_script ops[] = {
    	/* Disable PCI interrupt, enable Memory and Bus Master */
-		REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
+		REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
    	/* Enable ACPI mode */
    	REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
    		    LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),