[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Align chipset.cb with pci_devs.h

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48153 )

Change subject: soc/intel/alderlake: Align chipset.cb with pci_devs.h
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Patch Set 3:
> Patch Set 3:
> > Patch Set 3:
> >
> > @Subrata, can you give some comment for the EDS and the pci_devs.h are not identical?
> >
> > /* PCH Devices */
> > #define PCH_DEV_SLOT_SIO0	0x10
> > #define  PCH_DEVFN_THC0		_PCH_DEVFN(SIO0, 0)
> > #define  PCH_DEVFN_THC1		_PCH_DEVFN(SIO0, 1)
> > #define  PCH_DEVFN_CNVI_BT	_PCH_DEVFN(SIO0, 2)
>
> This is documentation issue, on ADL-P, we have THC0 as 0:0x10:0 where else on ADL-S its on 0:0x10:6 because I2C6 is on 0:0x10:0 there

So do we need to separate ADL-P and ADL-S in soc code? I think brya is use the ADL-P, will ADL-S be used for chrome or other coreboot project?