Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40260 )
Change subject: soc/intel/common: Add method to modify GPIO community PM config ......................................................................
soc/intel/common: Add method to modify GPIO community PM config
This patch adds CGPM, a helper method to configure GPIO power management bits that are part of miscellaneous config. This is needed for configuration of these bits on S0ix entry and exit.
BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto"
Signed-off-by: Venkata Krishna Nimmagadda venkata.krishna.nimmagadda@intel.com Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260 Reviewed-by: Venkata Krishna Nimmagadda Venkata.krishna.nimmagadda@intel.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/soc/intel/common/acpi/gpio.asl 1 file changed, 19 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Venkata Krishna Nimmagadda: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl new file mode 100644 index 0000000..364ac73 --- /dev/null +++ b/src/soc/intel/common/acpi/gpio.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * Configure GPIO Power Management bits + * + * Arg0: GPIO community (0-5) + * Arg1: PM bits in MISCCFG + */ +Method (CGPM, 2, Serialized) +{ + Local0 = GPID (Arg0) + If (Local0 != 0) { + /* Mask off current PM bits */ + PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG) + /* Mask in requested bits */ + PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG) + } +}