[coreboot-gerrit] Patch set updated for coreboot: 25aab46 exynos5420: Fix the way the rate of the input clock for i2c buses is found.

[Gabe Black]

Gabe Black ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3699

-gerrit

commit 25aab46e3fdf2c2c683ae36cc79ff148ae251567
Author: Gabe Black 
Date:   Sat Jun 22 19:43:40 2013 -0700

exynos5420: Fix the way the rate of the input clock for i2c buses is found.

The clock divider was being read from registers incorrectly which meant that
    the periph rate was wrong.

Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c
    Signed-off-by: Gabe Black 
---
 src/cpu/samsung/exynos5420/clock.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index e5ab001..8c4baf8 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -196,9 +196,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
    case PERIPH_ID_I2C9:
    case PERIPH_ID_I2C10:
    	sclk = get_pll_clk(MPLL);
-		sub_div = ((readl(&clk->clk_div_top1) >> 24) & 0x7) + 1;
-		div = (readl(&clk->clk_div_top0) & 0x7) + 1;
-		return (sclk / sub_div) / div;
+		div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1;
+		return sclk / div;
    default:
    	printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
    	return -1;