Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42874 )
Change subject: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42874/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42874/4//COMMIT_MSG@7 PS4, Line 7: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL
A bit off-topic.. […]
H1_PCH_INT_ODL is basically the net name for this signal. H1 is the chip name for Google Security Chip (https://2018.osfc.io/uploads/talk/paper/7/gsc_copy.pdf). PCH is platform controller hub. INT means that the signal is an interrupt line. _ODL is used for open drain signals.
These apply to how the signal is routed and used on the mainboard design and hence the abbreviations might not appear in soc/amd.
EEs working on different platforms (Intel, AMD, QC, Rockchip, etc.) seem to follow very different schemes for net names and hence the differences in coreboot comments/macros.