Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33182 )
Change subject: mb/google/sarien: Fix SSD's power off sequence before going to S5 ......................................................................
mb/google/sarien: Fix SSD's power off sequence before going to S5
BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin.
Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 2 files changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Roy Mingi Park: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 6eba2bc..4b05ba8 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -40,8 +40,9 @@
/* Clear SSD EN adn RST pin to avoid leakage */ If (Arg0 == 5) { - _SB.PCI0.CTXS (SSD_EN) _SB.PCI0.CTXS (SSD_RST) + Sleep(1) + _SB.PCI0.CTXS (SSD_EN) } }
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 6eba2bc..4b05ba8 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -40,8 +40,9 @@
/* Clear SSD EN adn RST pin to avoid leakage */ If (Arg0 == 5) { - _SB.PCI0.CTXS (SSD_EN) _SB.PCI0.CTXS (SSD_RST) + Sleep(1) + _SB.PCI0.CTXS (SSD_EN) } }